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PM related changes - #249
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plbossart
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Looks mostly good but multiple points are unclear or can be improved.
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@ranj063 let me know when you are a new version, I would like to test on top of some of my cleanups for module load/unload (where I still have the PM error message). |
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@plbossart @lgirdwood i've updated the PR based on previous comments now. |
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keyonjie
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in general, looks we are lack of taking controller out of reset at resume?
plbossart
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We are making progress, thanks for this update!
Couple of fixes requited, e.g. function renaming needed for clarity, some comments desired and need to address Keyon's comment. Let's try and close this week.
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@plbossart @keyonjie @lgirdwood all comments addressed now. |
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@ranj063 the code looks good to me but there was a conflict introduced with an earlier merge of Xiuli's work. Can you fix and resubmit? Thanks! |
The patch does the following: 1. Move the runtime_put call for the pci dev to its probe routine 2. Use pm_runtime_put_noidle and pm_runtime_get_noresume in pci probe/remove Signed-off-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
…r gating Add CGCTL/PGCTL bits that will be used for enabling/disabling clock gating and power gating respectively. Also, LP SRAM retention mode is enabled/disabled by BIT(4) of PGCTL register. So, fix the error in its name from PCI_CGCTL_LSRMD_MASK to PCI_PGCTL_LSRMD_MASK. Signed-off-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
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@plbossart fixed the conflict now! |
plbossart
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couple of typos and doubts I have on the PM sequences that are worthy of comments as well.
Add pre/post ops that will be called to perform actions before and after fw run routine. Signed-off-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
This patch defines pre/post fw run ops for SKL+ platforms. Disable clock gating, power gating and L1 support in pre_fw_run. Re-enable these in post_fw_run. Signed-off-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
This patch does the following: 1. Reset HDA controller during suspend so that the PGD1 can be power gated. 2.Take controller out of reset during resume 3. This patch modifies the hda_dsp_ctrl_link_reset() method so it can be called to reset the controller during suspend. Signed-off-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Runtime PM for sof device in enabled in pcm_probe() after the topology load has completed. So autosuspend should be called after pm_runtime_enable() here. Remove the call to autosuspend() in sof_probe as this should be done after topology load has been completed. Signed-off-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
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@plbossart fixed the typo and refs to fw_load now. |
plbossart
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ok let's merge and start a validation cycle.
Finish RISC-V support
This pull request includes these changes: