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Fix i2_s ARM CPU kernel: correct 128/32 weight-group layout (fixes #585) - #586
Alexander Hoffman (EUPHEMEME) wants to merge 1 commit into
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@microsoft-github-policy-service agree |
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Flagging that this is now an incomplete fix for When this PR was opened, the ARM #elif defined(__ARM_NEON)
#include <arm_neon.h>
#define QK_I2_S 64block now also appears in:
Both carry the identical Happy to extend this PR to cover both submodule sites, or to split them into a separate PR against the submodule repo — whichever you'd prefer. Just let me know. Separately, while testing this I found a live SIGSEGV on any i2_s model at |
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Verified on aarch64 against a reference: this PR fixes the output on its own base. Setup: Neoverse-N1, clang 18.1.3, PR head
The result is identical, window by window, to One caveat: current main ( Analysis assisted by Claude Code; all runs were executed and all numbers checked by me. |
The ARM CPU i2_s dot-product path decoded weights with a 64-weight / 16-byte group layout (QK_I2_S=64), but the gguf packs i2_s weights in the 128-weight / 32-byte layout used by dequantize_row_i2_s. It therefore read every weight matrix in scrambled order, producing wrong-but-finite output and garbage generation on all ARM CPU inference (Jetson / ARM-Linux, and Apple Silicon with -ngl 0; the default Metal path masks it). Replace the ARM branch of the ggml_vec_dot_i2_i8_s dispatcher with a correct 128/32-layout NEON decode (dotprod + scalar fallback); the x86/AVX path is unchanged. After the fix the CPU forward pass is bit-identical to the Metal/dequant path (modulo the expected int8-vs-f16 activation difference) and generation is coherent. Verified on a Jetson Orin Nano (aarch64). Fixes microsoft#585 Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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Rebased onto current This PR is not superseded by the submodule move. Matheus C. Feitosa (@matheus-c-feitosa) is right that the cmake build now runs the I2_S kernels from the submodule's Runtime confirmation, a second architecture. Matheus C. Feitosa (@matheus-c-feitosa) verified on aarch64 Linux (Neoverse-N1); adding arm64 Darwin. CPU-only build (no GPU offload) with this fix, official Identical to the Metal path on the same machine. (On Apple Silicon Metal masks the bug by dequantizing first, as the PR description notes — this is the CPU NEON path, where the bug is real.) One caveat for maintainers, with a control. Current
That's why the runtime receipt above is from a build at this PR's base pin (where it compiles) rather than a fresh build on Analysis assisted by Claude Code; all commands were executed and all output checked on the machine. |
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Thanks for the rebase and the Darwin run. You're right, and I should have been more precise: "no longer compiles this file" only holds for the CMake build that setup_env.py runs. At (Assisted by Claude Code.) |
Fixes #585.
What
The i2_s ternary CPU dot-product kernel unpacked weights with a 64-weight / 16-byte group layout, but the gguf packs them in the 128-weight / 32-byte layout (the one
dequantize_row_i2_suses). It read every weight matrix in scrambled order → wrong-but-finite output → garbage generation on all ARM CPU inference. On Apple Silicon the default Metal backend hides it (it dequantizes weights, so uses the correct layout); force CPU with-ngl 0and it reproduces, exactly like Jetson / ARM-Linux.Fix
Replace the ARM branch of the
ggml_vec_dot_i2_i8_sdispatcher with a correct 128/32-layout NEON decode (dotprod path + scalar fallback). The x86/AVX path is unchanged.Validation
[3] MUL_MAT "Qcur-0"(first ternary matmul, layer 0). With the fix, the full CPU forward pass is bit-identical to the Metal/dequant path, modulo the expected int8-vs-f16 activation-quantization difference (~0.3–1% per element).BitNet-b1.58-2B-4Ton a Jetson Orin Nano (aarch64, clang 14 / gcc 11) goes from!!!!to coherent English.See #585 for the full op-by-op trace and the in-kernel proof (the NEON arithmetic is correct; only the unpack layout was wrong).
Follow-up (not in this PR): the unused
_1xN/_Nx1/_1x4_32WARM sub-kernels and the ARM branch ofquantize_i2_sstill assume the 64/16 layout — dead on the inference read path for this model, but worth aligning.